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CY7C1071DV33 32-mbit (2 m 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-12063 rev. *h revised may 28, 2011 32-mbit (2 m 16) static ram features high speed ? t aa = 12 ns low active power ? i cc = 250 ma at 12 ns low complementary metal oxide semiconductor (cmos) standby power ? i sb2 = 50 ma operating voltages of 3.3 0.3 v 2.0 v data retention automatic power down when deselected ttl compatible inputs and outputs available in pb-free 48-ball fbga package functional description the CY7C1071DV33 is a high per formance cmos static ram organized as 2,097,152 words by 16 bits. the input and output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when: deselected (ce high) outputs are disabled (oe high) both byte high enable and byte low enable are disabled (bhe , ble high) the write operation is active (ce low and we low) to write to the device, take chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ) is written into the location specified on the address pins (a 0 through a 20 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 20 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appears on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see the truth table on page 10 for a complete description of read and write modes. io 0 ?io 7 row decoder sense amps data in drivers oe io 8 ?io 15 we ble bhe column decoder 2m 16 ram array ce a (10:0) a (20:11) logic block diagram [+] feedback
CY7C1071DV33 document number: 001-12063 rev. *h page 2 of 14 contents selection guide ................................................................ 3 pin configuration ............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 dc electrical characteristics .......................................... 4 capacitance ...................................................................... 4 thermal resistance .......................................................... 4 data retention characteristics ....................................... 5 ac switching characteristics ......................................... 6 switching waveforms ...................................................... 7 truth table ...................................................................... 10 ordering information ...................................................... 10 ordering code definitions ..... .................................... 10 package diagram ............................................................ 11 acronyms ........................................................................ 12 document conventions ................................................. 12 units of measure ....................................................... 12 document history page ................................................. 13 sales, solutions, and legal information ...................... 14 worldwide sales and design s upport ......... .............. 14 products .................................................................... 14 psoc solutions ......................................................... 14 [+] feedback
CY7C1071DV33 document number: 001-12063 rev. *h page 3 of 14 selection guide description -12 unit maximum access time 12 ns maximum operating current 250 ma maximum cmos standby current 50 ma pin configuration figure 1. 48-ball fbga [1] we a 11 a 10 a 6 a 0 a 3 ce io 10 io 8 io 9 a 4 a 5 io 11 io 13 io 12 io 14 io 15 v ss a 9 a 8 oe a 7 io 0 bhe nc a 17 a 2 a 1 ble io 2 io 1 io 3 io 4 io 5 io 6 io 7 a 15 a 14 a 13 a 12 a 20 a 18 a 19 3 26 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss note 1. nc pins are not connected to the die. [+] feedback
CY7C1071DV33 document number: 001-12063 rev. *h page 4 of 14 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied ... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc relative to gnd [2] ...............................?0.3 v to +4.6 v dc voltage applied to outputs in high z state [2] ................................. ?0.5 v to v cc + 0.5 v dc input voltage [2] ............................. ?0.5 v to v cc + 0.5 v current into outputs (low) .... .................................... 20 ma static discharge voltage ......................................... > 2001 v (mil-std-883, method 3015) latch up current .................................................... > 200 ma operating range range ambient temperature v cc industrial ?40 ? c to +85 ?? c 3.3 v ? 0.3 v dc electrical characteristics over the operating range parameter description test conditions -12 unit min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? v v ol output low voltage v cc = min, i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage [2] ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ? a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ? a i cc v cc operating supply current v cc = max, f = f max = 1/t rc, i out = 0 ma cmos levels ? 250 ma i sb1 automatic ce power down current ? ttl inputs max v cc , ce > v ih , v in > v ih or v in < v il , f = f max ?60ma i sb2 automatic ce power down current ? cmos inputs max v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0, v cc = v cc(max) ?50ma capacitance parameter [3] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3 v 16 pf c out i/o capacitance 20 pf thermal resistance parameter [3] description test conditions 48-ball fbga unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board 24.72 ? c/w ? jc thermal resistance (junction to case) 5.79 ? c/w notes 2. v il (min) = ?2.0 v and v ih (max) = v cc + 1 v for pulse durations of less than 20 ns. 3. tested initially and after any design or process changes that may affect these parameters. [+] feedback
CY7C1071DV33 document number: 001-12063 rev. *h page 5 of 14 figure 2. ac test loads and waveforms [4] data retention characteristics over the operating range parameter description conditions min typ max unit v dr v cc for data retention 2 ? ? v i ccdr data retention current v cc = 2 v, ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ??50ma t cdr [5] chip deselect to data retention time 0??ns t r [6] operation recovery time t rc ??ns figure 3. data retention waveform 90% 10% 3.0 v gnd 90% 10% all input pulses 3.3 v output 5 pf* including jig and scope (b) r1 317 ? r2 351 ? rise time: fall time: > 1 v/ns (c) output 50 ? z 0 = 50 ? v th = 1.5 v 30 pf* * capacitive load consists of all components of the test environment high-z characteristics: (a) > 1 v/ns 3.0 v 3.0 v t cdr v dr > 2 v data retention mode t r ce v cc notes 4. valid sram operation does not occur until the power supplies reach the minimum operating v dd (3.0 v). 100 ? s (t power ) after reaching the minimum operating v dd , normal sram operation begins to include reduction in v dd to the data retention (v ccdr , 2.0 v) voltage. 5. tested initially and after any design or process changes that may affect these parameters. 6. full device operation requires linear v cc ramp from v dr to v cc (min) > 50 ? s or stable at v cc (min) > 50 ? s. [+] feedback
CY7C1071DV33 document number: 001-12063 rev. *h page 6 of 14 ac switching characteristics over the operating range [7] parameter description -12 unit min max read cycle t power v cc (typ) to the first access [8] 100 ? ? s t rc read cycle time 12 ? ns t aa address to data valid ? 12 ns t oha data hold from address change 3 ? ns t ace ce low to data valid ? 12 ns t doe oe low to data valid ? 7 ns t lzoe oe low to low z [9] 1?ns t hzoe oe high to high z [9] ?7ns t lzce ce low to low z [9] 3?ns t hzce ce high to high z [9] ?7ns t pu ce low to power up [10] 0?ns t pd ce high to power down [10] ?12ns t dbe byte enable to data valid ? 7 ns t lzbe byte enable to low z [9] 1?ns t hzbe byte disable to high z [9] ?7ns write cycle [11, 12] t wc write cycle time 12 ? ns t sce ce low to write end 9 ? ns t aw address setup to write end 9 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 9?ns t sd data setup to write end 7 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [9] 3?ns t hzwe we low to high z [9] ?7ns t bw byte enable to end of write 9 ? ns notes 7. test conditions are based on signal transition time of 3 ns or less and timing reference levels of 1.5 v and input pulse leve ls of 0 to 3.0 v. test conditions for the read cycle use output loading shown in part (a) of figure 2 on page 5 , unless specified otherwise. 8. t power is the minimum amount of time that the power supply must be at typical v cc values until the first memory access can be performed. 9. t hzoe , t hzce , t hzwe , t hzbe and t lzoe , t lzce , t lzwe , t lzbe are specified with a load capacitance of 5 pf as in (b) of figure 2 on page 5 . transition is measured at ? 200 mv from steady-state voltage. 10. these parameters are guaranteed by design and are not tested. 11. the internal memory write time is defined by the overlap of ce , we = v il . chip enables must be active and we and byte enables must be low to initiate a write, and the transition of any of these signals can terminate the writ e. the input data setup and hold timing must be referenced to the leading edge of the signal that terminates the write. 12. the minimum write cycle time for write cycle 2 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback
CY7C1071DV33 document number: 001-12063 rev. *h page 7 of 14 switching waveforms figure 4. read cycle 1 (address transition controlled) [13, 14] figure 5. read cycle 2 (oe controlled) [14, 15] previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd t dbe t lzbe t hzce high impedance i cc i sb oe ce address data out v cc supply bhe , ble current notes 13. device is continuously selected. oe , ce , bhe or bhe or both = v il . 14. we is high for read cycle. 15. address valid before or similar to ce transition low. [+] feedback
CY7C1071DV33 document number: 001-12063 rev. *h page 8 of 14 figure 6. write cycle 1 (ce controlled) [16, 17] figure 7. write cycle 2 (we controlled, oe low) [16, 17] switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw t data i/o address ce we bhe ,ble t hd t sd t sce t ha t aw t pwe t wc t bw t sa t lzwe t hzwe data i/o address ce we bhe ,ble notes 16. data i/o is high impedance if oe or bhe , ble or both = v ih . 17. if ce goes high simultaneously with we going high, the output remains in a high impedance state. [+] feedback
CY7C1071DV33 document number: 001-12063 rev. *h page 9 of 14 figure 8. write cycle 3 (ble or bhe controlled) switching waveforms (continued) t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble we ce [+] feedback
CY7C1071DV33 document number: 001-12063 rev. *h page 10 of 14 truth table ce oe we ble bhe i/o 0 ?io 7 i/o 8 ?i/o 15 mode power h x x x x high z high z power-down standby (i sb ) l l h l l data out data out read all bits active (i cc ) l l h l h data out high z read lower bits only active (i cc ) l l h h l high z data out read upper bits only active (i cc ) l x l l l data in data in write all bits active (i cc ) l x l l h data in high z write lower bits only active (i cc ) l x l h l high z data in write upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 12 CY7C1071DV33-12baxi 51- 85191 48-ball fbga (8 9.5 1.2 mm) (pb-free) industrial ordering code definitions temperature range: i = industrial package type: bax = 48-ball fbga (pb-free) speed: 12 ns v33 = voltage range (3 v to 3.6 v) d = c9, 90 nm technology 1 = data width 16-bits 07 = 32-mbit density 1 = fast asynchronous sram family technology code: c = cmos 7 = sram cy = cypress c cy 1 - 12 bax 7 07 d i v33 1 [+] feedback
CY7C1071DV33 document number: 001-12063 rev. *h page 11 of 14 package diagram figure 9. 48-ball fbga (8 9.5 1.2 mm) ba48j, 51-85191 51-85191 *a [+] feedback
CY7C1071DV33 document number: 001-12063 rev. *h page 12 of 14 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor fpbga fine-pitch ball grid array i/o input/output oe output enable sram static random access memory ttl transistor transistor logic we write enable symbol unit of measure c degree celcius mhz mega hertz a micro amperes s micro seconds ma milli amperes mm milli meter ms milli seconds mv milli volts ns nano seconds ? ohms % percent pf pico farad vvolts wwatts [+] feedback
CY7C1071DV33 document number: 001-12063 rev. *h page 13 of 14 document history page document title: CY7C1071DV33, 32-mbit (2 m 16) static ram document number: 001-12063 rev. ecn no. submission date orig. of change description of change ** 605460 see ecn vkn new data sheet *a 1192183 see ecn vkn/kkvtmp removed ce 2 feature updated block diagram changed i cc spec from 160 ma to 225 ma changed c in spec from 8 pf to 10 pf changed c out spec from 10 pf to 12 pf changed t bw spec from 8 ns to 9 ns *b 2711136 05/29/2009 vkn/pyrs added 10 ns speed bin in 12 ns speed bin, changed i sb1 from 70 to 60 ma and i sb2 from 60 to 50 ma changed c in from 8 pf to 16 pf and c out from 10 pf to 20 pf changed ? ja from 28.37 ? c/w to 24.72 ? c/w removed 119-ball pbga package added 48-ball fbga package *c 2759408 09/03/2009 vkn/aesa removed 10ns speed marked thermal specs as ?tbd? changed t doe , t hzoe , t hzce , t dbe , t hzbe , t hzwe specs from 6 ns to 7ns added -12b2xi part (dual ce option) *d 2813370 11/23/2009 vkn changed i cc spec from 225 ma to 250 ma. *e 2925803 04/30/2010 vkn/aesa converted from preliminary to final removed dual ce option from the data sheet updated links in sales, solutions, and legal information *f 3109063 12/13/2010 aju added ordering code definitions . *g 3132969 01/11/2011 aju added acronyms and units of measure . changed all instances of io to i/o. updated in new template. *h 3268861 05/28/2011 aju updated functional description (removed ?for best practice recommendations, refer to the cypress application note an1064, sram system guidelines.?). [+] feedback
document number: 001-12063 rev. *h revised may 28, 2011 page 14 of 14 all products and company names mentioned in this document may be the trademarks of their respective holders. CY7C1071DV33 ? cypress semiconductor corporation, 2007-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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